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JP3418418B2 |
PURPOSE: To provide a conversion circuit in which the scale of a circuit and a power consumption can be reduced by operating format conversion with serial data as they are. CONSTITUTION: This circuit is equipped with a shift register 10 ...
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JP2003168982A |
To provide a signal transmission system which suppresses a noise strength caused in a signal transmission path between one substrate and the other substrate disposed so as to be alienated from each other and can cope with each individual...
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JP3411873B2 |
To solve problems of a conventional demultiplexer circuit with a byte synchronization function that has required a complicated design, had a limit in a pattern size and an insufficient timing margin and to provide a general-purpose circu...
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JP3409739B2 |
To provide an automatic skew adjustment device that can automatically adjust a skew between serial transmission lines, when using a plurality of the serial transmission lines for high speed parallel-serial conversion transmission. The au...
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JP2003143096A |
To provide a transmission system for data-compressing a digital video signal, and for operating word synchronizing data insertion and 8B/10B conversion, and for converting the data into serial data, and for transmitting the data so that ...
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JP2003122433A |
To achieve good transmission even if the length of wiring interconnecting an encoder for detecting the position information of a rotating machine or the like and a controller controlling the position and speed of the rotating machine usi...
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JP3399770B2 |
To provide a demodulation method and device for surely demodulating parallel data to be demodulated which are transferred in parallel from another semiconductor integrated circuit device. First and second parallel read data RD0, RD1 rece...
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JP3394159B2 |
To adjust an output bit width while suppressing a circuit scale of the interface circuit for a serial D/A converter. This circuit is provided with a phase modulator 24 that controls a phase of a control signal (word clock WCLK and LR clo...
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JP3388718B2 |
To provide a simply structured serial-parallel signal conversion input/ output device capable of carrying out the control of various driven apparatus with a serial signal in a batch or of changing respective output signals of various sen...
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JP2003078499A |
To provide a tone ordering circuit which can perform tone ordering with a small bit table.The tone ordering circuit which converts inputted serial data into parallel data of small bit width that a plurality of carriers can transmit data ...
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JP2003061114A |
To properly realize serial transmission of digital data configuring a 4:4:4 form HD signal and a D-Cinema signal whose quantization bit number exceeds 10 bits or the like by utilizing an existing circuit configuration component. A Y data...
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JP2003043111A |
To stably evaluate output data without using any special evaluation device in a semiconductor integrated circuit performing serial conversion of parallel data and outputting them at a high speed. In this semiconductor integrated circuit ...
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JP3374919B2 |
A serial/parallel converter includes a shift register arrangement (12', 12'' to 12n) and an output register arrangement (13', 13'' to 13n), each of which includes n storage devices (12', 12'' to 12n; 13', 13'' to 13n). Each of the storag...
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JP2003032121A |
To solve the problem of a VHDL(VHSIC hardware description language) description for an asynchronous serial-to-parallel conversion circuit adopting a conventional system that cannot normally drive a plurality of asynchronous serial-to-par...
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JP3371965B2 |
A system and method for sending multiple data signals over a serial link comprises an embedding unit and a removing unit coupled by a serial line. The embedding unit preferably receives a plurality of data streams, encodes the data strea...
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JP3370025B2 |
A switching apparatus comprising a centralized Switch Core (10) and at least one SCAL element for the attachment of Protocol Adapters. The Switch Core and the SCAL communicate to each other via n parallel serial links with each one trans...
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JP2003008448A |
To provide a data transmission method and device utilizing a means that can comparatively easily obtain serial transmission of digital data forming a progressive HD signal or the like through the use of existing circuit configuration com...
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JP2003008443A |
To provide a multiplexer that avoids a word alignment device of a serial parallel converter from being malfunctioned by a K28.5 code included in the lower-order 10-bits when multiplexing a plurality of gigabit Ethernet signals.The gigabi...
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JP3364777B2 |
To generate a PN pattern even when a clock has a high speed by reducing the number of output per circuit. This device has a code generation part generating n-parallel PN(pseudo random) codes and a parallel-serial conversion circuit 37 se...
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JP2003500884A |
The invention provides for an apparatus for decoding a serial datastream of channel words into a datastream of information words. The apparatus comprises an input terminal (10) for receiving the serial data stream of channel words, a ser...
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JP3360304B2 |
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JP3354597B2 |
A counter circuit comprises a Johnson-type counter (JC) including a plurality of flip-flops (FF1 SIMILAR FFn) connected in a cascade connection. Each flip-flop simultaneously receives a clock signal (CLK) at a respective clock input end ...
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JP3353543B2 |
PURPOSE: To suppress the extension of delay for control signal generation by providing a specific input control means and a specific OR means and circulating only one pulse sent from a bistable element in the first stage and taking out t...
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JP3352961B2 |
To decode sound data encoded by the encoding systems of different standards by absolute minimum circuits and to perform a delivery processing to a D/A converter. In the case of decoding the sound data encoded by the encoding system of a ...
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JP3350388B2 |
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JP3349017B2 |
To form a clock multiplex signal transmitted from a transmission device to a reception device in a simple clock circuit and to directly reproduce a clock signal from the received clock multiplex signal without using an expensive and comp...
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JP3345531B2 |
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JP3346945B2 |
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JP2002330439A |
To provide a transmitter for image information that can attain wireless transmission of the image information at a low rate independently of an operating system(OS).The transmitter for the image information includes an input section that...
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JP3341556B2 |
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JP3334466B2 |
To provide the parallel/serial conversion circuit from which data of a stable serial signal are outputted. When parallel signal data are received by a data input terminal DATA, the data are latched and inverted by a leading of a latch cl...
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JP3331087B2 |
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JP3329769B2 |
Processing apparatus (20) that directly samples and quantizes a complex envelope of a bandlimited waveform centered at a predetermined carrier frequency. An oversampling delta-sigma modulator (21) samples and quantizes the input signal t...
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JP3326789B2 |
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JP3325001B2 |
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JP3326137B2 |
A serial communication interface is provided in which the data length operating mode is selectable. Based on the selected data length operating mode, serial-to-parallel and/or parallel-to-serial conversion takes place in data blocks of t...
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JP2002232300A |
To reduce power consumption by reducing the number of times of access to a memory.Serially inputted data are converted to the parallel data of (n) ((n) is an integer ≥2) bits by a serial/parallel converter and after the converted paral...
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JP2002223203A |
To achieve high-speed data transmission by a method of transmitting data by which a plurality of bit data is transmitted by converting the data into a plurality of serial data by means of a plurality of parallel-to-serial conversions by ...
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JP2002217742A |
To provide a serial-parallel(S/P) converter that is in operation even when number of output channels is an even number or an odd number.The serial-parallel converter comprises 1:2 serial-parallel(S/P) conversion circuits 1-3, 5, 6, D fli...
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JP2002204448A |
To provide a dot de-interleave circuit at a reduced cost by eliminating the need for a RAM and decrease the circuit scale.In the circuit applying parallel serial conversion adopting the dot de-interleave system to received signals INA, I...
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JP3301229B2 |
PURPOSE: To simplify circuit configuration, to decrease the assembly process of the device and to improve maintainability by performing exclusive ORing and transmitting power and data signals to a serial signal receiver. CONSTITUTION: A ...
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JP2002198944A |
To transmit serially a sending data of more than 2 bites constitution efficiently without increasing the number of transmitting lines.In this system, a clock data generating circuit 35 outputs a bit-sequence of '1, 0, 0, 0, 0, 0, 0, 0' a...
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JP2002190736A |
To reduce power consumption.The first and second sampling circuits for sampling an input signal and an arithmetic amplifier for performing the arithmetic amplification of an input signal sampled by these sampling circuit are provided. Th...
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JP2002176409A |
To provide a demultiplexer for a time division multiplex signal that can demultiplex channels even when a serial signal at a high bit rate is received through a high-speed serial signal.In the demultiplexer for a time division multiplex ...
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JP2002176362A |
To efficiently multiplex-transmit the digital video signals of a plurality of systems and the digital audio signals of a plurality of systems by a means which is comparatively easily arranged and to reduce cost.S/P conversion is performe...
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JP2002171298A |
To improve the reception performance and the transmission efficiency including decoding and retransmission on the reception side.An S/P conversion part 101a converts transmission data A from serial data to parallel data and outputs this ...
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JP2002164791A |
To provide a CRC code arithmetic circuit and a CRC code operating method which suppress the number of used CRC code arithmetic circuits and operate CRC codes from 4n-byte parallel data inputted as variable length data.This CRC arithmetic...
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JP2002164507A |
To enable the ratio of effective area of a chip to be increased and simplify test work by reducing wiring inside and outside a semiconductor chip and the number of electrode pads necessary for the semiconductor chip.Serial/parallel conve...
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JP2002152053A |
To provide a parallel-serial conversion circuit that can reduce power consumption while suppressing skew and jitter of a data signal and a strobe signal to the utmost.FF 10A-10H latch data D0-D7 synchronously with a clock signal CLK50 wi...
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JP2002135773A |
To provide an image processor capable of suppressing enlargement of circuit scale even if the setting of retrieval range is enlarged and also enables correlational calculation processing between image in real-time.In the image processor ...
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