| Document |
Document Title |
|
JP2001078468A |
To control the output of a high-voltage outputting device with serial data without causing circuits to malfunction. A high-voltage outputting device is provided with a controller 1, which generates serial control data, a shift register 2...
|
|
JP3148445B2 |
PURPOSE: To obtain a multiplexer circuit with a synchronizing function whose constitution is relatively simple with the highest operating speed. CONSTITUTION: A phase comparator circuit 2 detects the phase mismatching of a timing signal ...
|
|
JP2001069181A |
To provide a digital data transmitting method and a device to carry out the same with which continuation of signals at a fixed level is suppressed while keeping a transmission band as conventional by performing mBnB block encoding to tra...
|
|
JP3145988B2 |
To reduce skew of a clock signal CLK in an internal circuit and to prevent a critical path from being formed when a clock speed is high. A plurality of 1/2 serial/parallel conversion units 31-1, 32-1, 32-2, 33-1-22-4, 34-1-34-4 are conne...
|
|
JP3135990B2 |
PURPOSE: To provide the parity adding circuit having a circuit configuration by which a circuit scale of a parity arithmetic circuit can be made small, and also, its processing speed can be increased. CONSTITUTION: When both of a selecto...
|
|
JP3136422B2 |
A limiting factor in the operating speed of a bit-serial integrated circuit is the stray capacitance associated with interconnections of functional elements on the integrated circuit, which stray capacitance tends to be significantly lar...
|
|
JP2001044851A |
To ensure timing margin of serial parallel conversion at an output stage, even when the timing adjustment for a parallel clock and a serial clock is difficult in the configuration, where parallel input data are parallel-serial converted ...
|
|
JP2001044852A |
To realize comparatively easy data transmission by obtaining first and second division 20-bit word string data, having a second word transmission rate from 20-bit word string data having the first word transmission rate, executing replac...
|
|
JP3134449B2 |
PURPOSE: To provide a serial/parallel conversion circuit reduced at the number of gate circuits required for its constitution. CONSTITUTION: Each of register blocks F00 to F33 is constituted of an R-S flip flop(FF) consisting of plural N...
|
|
JP3133601B2 |
A parallel-to-serial conversion device capable of improved space efficiency has a corner turn memory array provided in an input section of the device to perform parallel-to-serial conversion by writing in row direction of the input secti...
|
|
JP3130344B2 |
The device 15 for serialising words of N bits SYNC, OP, D0-D7 produces N clock signals CL0-CL9 of period T which are successively delayed by T/N in order to operate respective registers 36, 38, 39 in respect of the successive outputting ...
|
|
JP2001024517A |
To transmit digital word string data such as an HD digital video signal for progressive scanning by a means which can be comparatively easily prepared without requiring development of a new circuit element or the like.A digital video sig...
|
|
JP2001024518A |
To make it possible to convert also a parallel data signal having no periodicity by using a parallel/serial(P/S) conversion clock making it unnecessary to adjust periodical deviation from a parallel signal.A P/S conversion clock 7 having...
|
|
JP2001016280A |
To comparatively easily arrange the transmission of 10-bit word train data by changing compound 10-bit word train data having a part based on an additional word data group, which includes a 10-bit reference word, into serial data and tra...
|
|
JP2001007710A |
To provide a digital signal transmission system for quickly operating signal transmission which can be applied to a digital image pickup device in a surface flaw detecting device for detecting the surface flaw of steel, which is several ...
|
|
JP2000349834A |
To obtain an asynchronous serial information receiver and an asynchronous serial information transmitter on the basis of asynchronous serial information transmission reception system by setting a baud rate in the asynchronous serial info...
|
|
JP2000349651A |
To reduce the total power consumption of a semiconductor circuit by supplying the power voltage according to the operating frequency of every circuit block.An MUX circuit 100, for example, consists of MUX circuits 111-114, 121, 122 and 1...
|
|
JP3116679B2 |
PURPOSE: To prevent slip from being generated at the time of conversion by starting the operation of a fixed cycle circuit with the output of a differentiation circuit and supplying a signal in a fixed cycle to a serial conversion circui...
|
|
JP3115756B2 |
PURPOSE: To attain high bit rate operation by detecting a start signal included in binary mode serial data to be received and converting the serial data into parallel data while using the detected start signal for a start point. CONSTITU...
|
|
JP2000516054A |
The invention relates to fast serial-parallel and parallel-serial converters, and in them included frequency dividers. The serial-parallel converter comprises a shift register, an output register and a frequency divider. The parallel-ser...
|
|
JP2000315147A |
To provide a data rate conversion circuit capable of converting a data rate without being influenced by the timing of input and output clock signals and without generating an error in output data. A counter 10 counts up input clock signa...
|
|
JP3107555B2 |
|
|
JP3105584B2 |
PURPOSE:To acquire a common control signal for control of the write of a storage circuit and also to simplify the structure of a serial/parallel signal converter circuit despite the increase of the output data signals. CONSTITUTION:A sto...
|
|
JP2000307434A |
To transmit a digital signal of SMPTE-125M or a signal or based upon it by using a unshielded twisted pair cable. A clock signal of SMPTE-125M is multiplied by a multiplier 105. A 10-bit parallel signal is selected by selectors 107 and 1...
|
|
JP2000295114A |
To transfer serial data with a variable length by using two signal lines. Two signal lines 111, 112 interconnect a serial data transmission circuit 100 and a serial data reception circuit 110. The serial data transmission circuit 100 has...
|
|
JP3099564B2 |
|
|
JP2000286695A |
To provide a divider circuit which is suitable to divide a reference clock into the one-over-integer value that is not equal to the n-th power of 2 by feeding the output of a logical gate that provides AND between this output and a reset...
|
|
JP3096801B2 |
|
|
JP2000278141A |
To provide a multiplexer that can be operated at a faster speed. Flip-flop circuits 1-4 are interposed between a control signal generating circuit 32 and a 4:1 selector 37, and a flip-flop 5 is interposed between a 1/4 frequency divider ...
|
|
JP3094973B2 |
To provide a signal synchronizing detection circuit which reduces data delay in the case of signal synchronizing detection while surely performing serial/parallel(S/P) conversion, is composed of a circuit in a comparatively small scale a...
|
|
JP2000269823A |
To obtain a semiconductor integrated circuit that can test an internal circuit of a semiconductor chip mounted with a serial/parallel converter employing a PLL circuit without increasing the number of test purpose external input terminal...
|
|
JP2000259297A |
To store states of each electrical node of a transmission line and to initialize them at the start of operation of a computer. A device including a signal transmitting circuit 12 to form a stream of continuous bits, the sufficiently long...
|
|
JP3087928B2 |
PURPOSE:To shorten processing time by providing address designating means giving a memory section an address for segmenting a data at a set code length and sequentially outputting or storing the data thus sectioned, thereby, eliminating ...
|
|
JP2000252839A |
To provide a parallel/serial conversion circuit that copes with a low frequency and converts parallel data into serial data at a low cost, with a simple circuit configuration. When converting n-bit parallel data into serial data, a decod...
|
|
JP3083738B2 |
This disclosure sets forth the use of input 2-bit encoders to form an encoder network capable of handling any number of encoder inputs by using the VALID output of each input 2-bit encoder as a data input to a later stage encoder and to ...
|
|
JP2000235527A |
To collect the operation history of a controlled target based on control information sent from a control part to the controlled target. The saved wiring unit for simplifying wiring by serially transmitting a signal between a device contr...
|
|
JP2000236264A |
To increase flexibility of processing, while improving the data processing efficiency and the redundancy of the processing, reducing the DC power consumption, and making a circuit small-sized by making nibble/byte converters, dibit/byte ...
|
|
JP2000232370A |
To reduce the numbers of input-output pins and signal lines. One of six parallel-serial conversion circuits 51 synchronizes a parallel composite signal CMP-P with 8-bit width inputted in 13.5 MHz frequency with a bit clock B-CLK outputte...
|
|
JP3072494B2 |
|
|
JP2000207848A |
To prevent a reference amplitude level from being converged to an inappropriate value. A reference amplitude level adaptive updating means 1a updates adaptively a reference amplitude level based on levels of a discriminated result and a ...
|
|
JP3068077B2 |
|
|
JP3068593B1 |
The first present invention provides a serial-parallel converter which comprises: a plurality of data extraction units for sequentially extracting different bit values of serial data, which are sequentially inputted, for individually hol...
|
|
JP3068394B2 |
PURPOSE:To greatly reduce wire harness, reduce the size of application software, and make the substrate area small by coupling plural sensors with a control microprocessor by a serial bus. CONSTITUTION:Data read by sensors 2 of serial ad...
|
|
JP2000196462A |
To secure a setup margin and to enable high-speed operation by reading parallel data out of a flip-flop(F/F) according to a signal with the change point of input parallel data as a reference. An edge detecting signal TPG of a timing puls...
|
|
JP2000195287A |
To reduce power consumption of a shift register and to reduce the occupancy area of chips. By providing gate circuits 11, 12 for guaranteeing minimum delay in same phase transfer to a second flip-flop circuit (FF-4) from a first flip-flo...
|
|
JP3063433B2 |
|
|
JP2000152280A |
To provide an image pickup system that uses a P/S converter, an S/P converter, an E/O converter and an O/E converter in a transmission section of an image pickup system where an interlaced scanned image with 1125 vertical scanning lines ...
|
|
JP2000151390A |
To output a clock signal which has a prescribed duty and is synchronized with an input signal by forming the clock signal having the desired duty, based on the output signal of a latching means latching an input signal with a reference c...
|
|
JP2000151423A |
To provide a parallel/serial conversion device which can transfer desired data width with simple constitution by installing an outer unit control means which transfers in series data of the prescribed number of bits, outputs a latch sign...
|
|
JP2000151568A |
To change over a plurality of serial transmission systems without causing hit of data in a device that transmits the data while switching a plurality of the serial transmission systems. Parallel data outputted from an S/P conversion circ...
|
