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JP2763709B2 |
PURPOSE: To provide a bit/dibit converting circuit of a simple constitution which is suited to a high speed operation. CONSTITUTION: A 2-divider 11 is provided to divide a bit rate clock into two clocks together with a synchronizing pres...
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JPH10135844A |
To improve the reliability of outputted parallel data without remarkable increase in number of components. Serial data (a) received from a 1st device 1 are given to a 1st serial/parallel (S/P) conversion section 22, and the 1st parallel ...
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JPH1098458A |
To provide the SYNC word detection circuit by using a few logic gates so as to detect a SYNC word easily. A high level (that is, '1') bit signal of a SYNC word is given to an AND gate AND1 of a 1st logic gate 2, and a low level (that is,...
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JPH1075182A |
To prevent the output of a parallel-serial converting part from being interrupted, by using an inexpensive storage memory even in a refresh cycle. This device is provided with a storage memory 1 for storing data, controlling part 2a for ...
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JPH1075183A |
To suppress the increase of a data storage buffer amount by respectively separately developing in parallel the input data of a part corresponding to a bit number divided in the case of dividing the data length of serial input data by a p...
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JPH1063617A |
To provide a serial communication device capable of corresponding to plural kinds of CPUs having respectively different data bus width, improving the efficiency of data transfer by fully utilizing the data bus width and capable of transf...
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JP2718600B2 |
PURPOSE: To miniaturize the entire scale of a synchronizing signal detecting circuit by inputting a serial signal being a CD-ROM signal including a synchronizing signal by 16 bit units. CONSTITUTION: The output of a 16 bit serial registe...
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JPH1051319A |
To provide an image signal processing unit in which parallel data are converted into serial data without the need for a clock signal with a higher frequency than a frequency of a picture element clock. In addition to means 2-8 recovering...
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JPH1049487A |
To provide data transfer equipment without generating skew, cross talk, etc., even in high speed data transfer, unlocking a PLL circuit even when a high speed serial transfer element using the internal PLL circuit is used and hardly infl...
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JP2715900B2 |
PURPOSE: To correct the error or bytes longer than the byte length of a code and to reduce the scale of an encoding and decoding circuit in the parallel data transmission equipment using the byte error correction code. CONSTITUTION: (i),...
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JP2712304B2 |
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JP2706005B2 |
PURPOSE: To obtain the parallel serial (serial parallel) conversion circuit in which a frequency divider circuit is operated smoothly at a high speed even when the number of parallel input signals is increased with a small circuit scale....
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JPH1022838A |
To attain high-speed transmission partially, even when numbers of parallel data are numerous by connecting a serial transmission terminal of other transmission unit to a parallel input terminal of a transmission unit and giving parallel ...
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JPH1011368A |
To write only data inside a frame without writing error data in FIFO by providing a control part, etc., for controlling a serial data receiving part, a writing control signal generating part and a buffer memory. When an error occurs by a...
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JPH1013986A |
To finely control sound volume of a loudspeaker by simplified and low cost speaker structure, when a driving coil of the loudspeaker such as an electromagnetic coupling speaker is driven by a digital audio signal. A primary coil of a spe...
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JPH1013373A |
To reduce the scale of the hardware while keeping high compatibility with an existing device in the case of applying a bus configuration of an existing time division multiplexer to a small capacity time division multiplexer. A data memor...
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JPH1013384A |
To allow the transmitter to be restored after a prescribed processing without immediately automatic restoration when a transmission error is solved by keeping an output corresponding to an error state till a reset signal is given to a re...
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JP2559237Y2 |
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JPH09331260A |
To increase the operating speed of a logic integrated circuit device, etc., containing a serial to parallel converter incorporating an edge trigger type flip flop and to reduce the cost of the device, etc., by increasing the operating sp...
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JPH09331321A |
To provide the synchronization circuit in which mis-detection or missing of detection of a synchronizing signal is reduced even when serial data are read at a high speed from a high density recording optical disk. In the synchronization ...
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JP2692476B2 |
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JPH09321732A |
To transmit data without receiving the influence of frequency characteristic. In a transmitter 10, after a base band binary data S is serial- parallel-converted by a serial-parallel converter 11 and reverse-Hadamard- transformed by a rev...
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JPH09321774A |
To enable data exchange to be executed, where a pre-existing parallel data processing system is utilized as it is by making the processing unit of serial data immediately before serial/parallel conversion match the processing unit of par...
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JP2689379B2 |
A serial bit stream (10) and a clock signal (14) at a frequency equal to the bit rate divided by an integer n are passed in opposite directions via respective delay lines (31-37, 41-47) to respectively the data (D) and clock inputs (C) o...
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JPH09311159A |
To monitor a parallel/serial conversion circuit with a simple structure. At the time of taking parallel data in a shift resistor 2 for serial conversion, the added parity bits are taken in a parity bit housing F/F4. EXOR of data sent out...
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JPH09307457A |
To halve a frequency of a basic clock pulse to be applied for drive at the same data rate by detecting a rising edge of the basic clock pulse and a rising edge of an inverted pulse respectively. From a parallel data input terminal 1, n-b...
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JPH09307440A |
To conduct digital correction with a simple configuration by setting a correction value of a most significant bit, halving the correction value for each clock input and repeating further halving the halved value. An object maximum value ...
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JP2676077B2 |
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JPH09284247A |
To demultiplex data for plural ports as serial data from a parallel data transmission line in which plural port data are subject to time division multiplexing. Eight bit parallel multiplex data D0-D7 are given to individual shift registe...
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JP2666704B2 |
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JP2664239B2 |
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JPH09261079A |
To convert serial analog data subject to multi-time division into parallel data and to provide an output of the data with a simple circuit configuration while keeping pair performance of the analog data. This circuit is made up of a seri...
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JP2655509B2 |
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JPH09247116A |
To surely recover synchronization in a short time at the time of an asynchronization state in the midst of an operation with respect to the serial/ parallel converting circuit and its synchronization circuit. The plural serial/parallel c...
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JPH09246977A |
To make the scale of a circuit small and to reduce the burdens of a CPU while maintaining the balance of processing burdens distributed to a hardware and a software. In the case of varying a bit transmission speed and performing receptio...
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JPH09246993A |
To eliminate the fetching of erroneous data due to noise or the like generated in inserting/detaching a transmission side package by using enable signals turned significant only in a period for the valid data length of reception data and...
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JPH09246992A |
To improve encoding efficiency and to reduce a memory capacity for Markov modeling. A dictionary inside a dictionary memory 12 is switched by a symbol immediately before stored in an (n)-bit register 11 and an index storing the symbol in...
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JP2654452B2 |
Apparatus and associated methods are disclosed for converting asynchronous nonhomogeneous variable width parallel data pattern signals to serial data pattern signals representative of said input signals and suitable for transmission over...
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JPH09237113A |
To prevent erroneous detection even if a signal where a specified cycle pattern is parallel expanded is inputted. Parallel signal lines are monitored by change point detecting circuits 210-213, input disconnection is detected so as to ad...
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JPH09232969A |
To minimize a damage by providing a rewritable emergency processing table to a RAM so as to execute emergency processing quickly independently of the communication procedures and the communication speed. A serial parallel converter 2r us...
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JP2648010B2 |
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JP2641999B2 |
In order to detect the format of asynchronously, serially transmitted character data using a command signal which includes a plurality of command character data, wherein the beginning of each of the command character data is identified b...
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JPH09214565A |
To permit a data transmission device to make data written into a buffer memory in a word unit constituted by plural bits into serial data of variable length burst, in which the same code continuation is suppressed, so as to transmit it a...
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JP2638144B2 |
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JP2637992B2 |
A remote control system comprises a central control station and at least one local station installed remotely from the central control station and connected thereto through a power transmission line. The local station has a plurality to ...
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JPH09200058A |
To reduce the number of circuits for high speed pulse width modulation(PWM) by adopting the configuration for parallel serial/serial parallel conversion to PWM processing in an image processing unit. A recovered clock signal whose duty i...
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JPH09200059A |
To avoid occurrence of malfunction due to different length of each bit signal line in the layout design at development of an LSI. A parallel address signal PA outputted from an address generating circuit is given to a P/S converter circu...
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JPH09186681A |
To prevent mis-synchronization in coding by converting the number of bits in a prescribed bit unit into conversion data in different bit number, adding a frame synchronization code to the data, converting the conversion data into a trans...
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JPH09181577A |
To provide a circuit which is capable of generating a PN parallel pattern by using plural of the same PN parallel pattern generation circuits. By using the same parallel pattern generation circuits 10-1 to 10-4 generating 32-bit parallel...
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JPH09161400A |
To attain a high speed data processing and the reduction of power consumption of a processing circuit by constituting a circuit with a serial- parallel conversion circuit and the scramble releasing circuit of parallel processing. The scr...
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