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WO/2018/128851A2 |
Technology for a next generation node B (gNB) operable to measure crosslink signal-to-interference ratio (SINR) in a dynamic time division duplex (TDD) new radio (NR) system is disclosed. The gNB can encode a downlink interference measur...
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WO/2018/125232A1 |
Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry ...
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WO/2018/120549A1 |
Disclosed is a method for processing a time stamp in an EPON, the method comprising: detecting a delay in an MPCP packet passing through a PCS and a delay in same passing through an MAC coding layer; acquiring a first time stamp carried ...
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WO/2018/120173A1 |
Provided is a method for exchanging a time synchronisation message. The method comprises: a network device exchanging a clock synchronisation message with a first clock source, wherein the network device comprises a boundary clock; the n...
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WO/2018/123857A1 |
In the present invention, when a data collection terminal slave device (2) receives a dummy packet the data collection terminal slave device appends to a return packet a timestamp indicating the reception time of the dummy packet and a t...
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WO/2018/118261A1 |
Disclosed is a method of synchronization signal correlation, comprising receiving a synchronization signal ("SS") on a plurality of receive antennas; performing a signal revision on the SS received on a first receive antenna, the signal ...
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WO/2018/117005A1 |
The purpose of the present invention is to improve data quality by reducing the influence of jitter or noise in a series of processes from oversampling to demodulation of a data bit string, and performing a correct data decoding process ...
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WO/2018/112903A1 |
Disclosed in the present application is a clock synchronization method, relating to the field of communication technologies. The method comprises: acquiring a first sequence, the first sequence being a part of a to-be-received sequence o...
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WO/2018/108837A1 |
The invention relates to a method for the detection, by a receiver device, of a pulse of a signal received by said receiver device, said received signal corresponding to data emitted with a predetermined period Tc, each data item being e...
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WO/2018/110475A1 |
[Problem] To provide a reception device in which MMTP packets can be recovered in an appropriate order even when a leap second is inserted. [Solution] A recovery unit 36 recovers data from a MMTP packet transmitted by a transmission devi...
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WO/2018/108288A1 |
A phase interpolator (100) to receive a first and a second input clock (110, 120) with a first and a second input clock edge (111, 121) comprises an interpolating circuit unit comprising: resistors (153a, 153b) in parallel; for each resi...
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WO/2018/112310A1 |
Certain aspects of the present disclosure relate to techniques for estimating a channel using soft-windowing. A user equipment (UE) may determine, based on a cyclic prefix (CP) length of a channel, a timing window for sampling reference ...
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WO/2018/102034A1 |
In accordance with embodiments disclosed herein, there is provided systems and methods for link training between a host device and a device. The host device includes a clock source, front-end circuitry, a duty cycle monitor (DCM), link t...
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WO/2018/099048A1 |
Disclosed in an embodiment of the present invention are a method and device for processing a time stamp, and a storage medium. The method comprises: receiving a first packet, and acquiring, from the first packet, a data frame and time st...
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WO/2018/101369A1 |
Provided is a system with which time synchronization can be realized for a plurality of devices that are disposed at positions where a GNSS signal cannot be received. A time synchronization system comprises: a reference time acquisition ...
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WO/2018/099375A1 |
Disclosed in the embodiments of the present disclosure are a synchronization method, a synchronization device, a synchronization apparatus and a system. The method applied in a first device comprises: synchronizing the first device with ...
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WO/2018/096548A1 |
A method for measuring one-way delays in a communications network, the method comprising: maintaining a virtual clock state comprising information for converting times measured with respect to remote clocks into times as would be measure...
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WO/2018/098084A2 |
A ring network architecture includes multiple communication nodes configured in a ring. Wave pipelining is used to provide for high bandwidth and low latency on-chip communications. Each node implements a source-synchronized clocking sch...
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WO/2018/097800A1 |
Embodiments of the present invention provide a method and system for timing related tasks in IoT systems, for example, in relation to synchronisation of clocks and timestamping. It is desirable that the method and system is able to withs...
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WO/2018/097418A2 |
The present invention relates to a method for synchronization of slave devices and, more specifically, to a method for synchronization of slave devices having, in addition to unique IDs, virtual IDs received from a master device.
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WO/2018/091976A1 |
The invention comprises a videoconference server (2) comprising : - an audio processing module (9) configured to, o calculating an average audio processing delay of processing audio packets intended to the second client device, in order ...
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WO/2018/093811A1 |
The systems and methods of the present disclosure utilize an advantageous data transmission protocol, which facilitates determining and compensating for transmission delay between nodes in a communications network in order to correlate t...
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WO/2018/089673A1 |
Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of s...
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WO/2018/082665A1 |
Provided is a frequency synchronization method. The method comprises: a slave clock receives a first pulse signal and a second pulse signal; the slave clock determines that a frequency deviation of the slave clock with respect to a maste...
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WO/2018/081353A1 |
System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel ch...
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WO/2018/080652A1 |
An example method of performing an eye-scan in a receiver includes: generating (104) digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference cloc...
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WO/2018/081010A1 |
Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. One method includes providing a plurality of launch clock signals, including launch clock signals having a different phase shift...
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WO/2018/076864A1 |
Disclosed in the embodiments of the present invention are a data synchronization method, apparatus, storage medium and electronic device. The data synchronization method comprises: determining a data type corresponding to target data to ...
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WO/2018/077302A1 |
Provided are a channel clock synchronization method and device. The method comprises: respectively acquiring a clock signal and a service signal, and using two channels to respectively process the clock signal and the service signal; and...
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WO/2018/076651A1 |
Disclosed in embodiments of the present invention are a time synchronization method, a device and a computer storage medium: acquiring a first time stamp of a second time processing unit of a second device sending a first report; determi...
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WO/2018/073666A1 |
According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first c...
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WO/2018/068824A1 |
The present invention relates to an apparatus and method for deskewing an eye diagram of a multilevel signal, wherein an eye skew value of each signal level of the multilevel signal is first estimated at a respective sampling phase using...
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WO/2018/067785A1 |
Serial data transfer uses ever increasing transmission rates. The data transfer rate of a clock-and-data recovery (CDR) deserializer can be increased by using multiple independent sampler blocks that process serial input data in parallel...
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WO/2018/064895A1 |
Aspects of the disclosure provide an apparatus that includes a baseband processing circuit and a transmitting circuit. The baseband processing circuit is configured to encode a reference signal based on a specific sequence to generate a ...
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WO/2018/059671A1 |
The present invention relates to an apparatus and method for recovering clock and data from an M-level signal of a receiver in a transmission system, M being a positive integer and a power of two, wherein an M-level log2(M)-bit analog-to...
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WO/2018/056781A1 |
A local clock skew correction device of the present invention is a client device which is synchronized with a counterpart client device so as to provide a time-aware service, and comprises: a local time providing unit for providing first...
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WO/2018/053747A1 |
The application discloses a resource sharing method, a network node, and an associated apparatus. The method comprises: upon a fault of a service occurring in a working route, and a fallback route being adopted for data transmission, det...
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WO/2018/057122A1 |
A method for increasing an accuracy of a transceiver loopback calibration includes determining a time difference between the use of a local oscillator signal by a second mixing circuit within a receive path of the transceiver and the use...
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WO/2018/056138A1 |
The present invention allows a system clock, a media clock, and the like to be highly accurately synchronized between devices. A wireless device is provided with a main control unit and a wireless control unit. Association information of...
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WO/2018/057259A1 |
An SoC integrated circuit package is provided in which the analog components of a SerDes for an SoC die in the SoC integrated circuit package are segregated into a SerDes interface die in the SoC integrated circuit package.
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WO/2018/055746A1 |
A base station (110) generates a first code string that is obtained by cyclically shifting a predetermined code string by an amount corresponding to a difference between a first time section and a transmission reference timing of a wirel...
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WO/2018/045857A1 |
One aspect of the disclosure is directed to a system and method for determining the propagation delay for a signal to traverse an optical fiber between two transceivers. The method is performed by a first network element and includes tra...
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WO/2018/049280A1 |
Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial dat...
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WO/2018/046596A1 |
The apparatus for actuating electrical and/or electronic components of a motor vehicle model, in particular an interior light and/or exterior light, such as e.g. a tail light module of a motor vehicle, is provided with a differential two...
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WO/2018/042837A1 |
According to the present invention, Fourier transform is performed on a reception signal to obtain a first calculation value. Fourier transform is performed on a known signal to obtain a second calculation value. The first calculation va...
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WO/2018/045088A1 |
A system or a network may include an optoelectronic module that includes an optical transmitter optically coupled with an optical fiber, and a controller communicatively coupled to the optical transmitter. The controller may be configure...
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WO/2018/041228A1 |
A method, device and system for transferring synchronization information. The method may comprise: a transmitting end selects at least one Ethernet physical layer link (PHY) from a flexible Ethernet group (FlexE group) for transferring s...
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WO/2018/040011A1 |
A clock recovery apparatus (300) and a clock recovery method. In the clock recovery apparatus (300), a signal clock compensator (301) is configured to adjust clock phases of a first signal and a second signal in the frequency domain acco...
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WO/2018/035719A1 |
Embodiments of the present application provide a method for acquiring a phase discrimination signal in a clock recovery circuit and a phase discriminator, which are used for acquiring a correct phase discrimination signal. The technical ...
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WO/2018/038838A1 |
An apparatus is provided which comprises: an amplifier; a first slicer coupled to the amplifier; a de-serializer coupled to an output of the first slicer; a multiplexer which is operable to select one of data or a test signal for the amp...
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