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Patent Searching and Data


Title:
【発明の名称】電流ミラー回路
Document Type and Number:
Japanese Patent JP2002530971
Kind Code:
A
Abstract:
Current mirror circuit including a current input terminal (2), a current output terminal (6), a common terminal (8), a first transistor (T1) arranged between the current input terminal (2) and the common terminal (8), a second transistor (T2) arranged between the current output terminal (6) and the common terminal (8), a transconductance stage (TS) having an input terminal coupled to the current input terminal (2), and an output terminal coupled to the common terminal (8), and a bias source (22) for biasing the control electrodes of the first and second transistors (T1, T2). This configuration provides a large bandwidth independently of the input current, accurate current transfer and a single pole system.

Inventors:
ハサーン、グル
ヨハネス、ピー.エー.フランバッハ
Application Number:
JP2000584361A
Publication Date:
September 17, 2002
Filing Date:
November 11, 1999
Export Citation:
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Assignee:
コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ
International Classes:
G05F3/26; H03F3/343; (IPC1-7): H03F3/343; G05F3/26
Attorney, Agent or Firm:
佐藤 一雄 (外3名)