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Title:
歪みシリコン・オン・インシュレータ(SSOI)およびこれを形成する方法
Document Type and Number:
Japanese Patent JP2007521628
Kind Code:
A
Abstract:
A method for fabricating a strained Si layer on insulator, a structure of the strained Si layer on insulator, and electronic systems comprising such layers are disclosed. The method comprises the steps of forming epitaxially a relaxed SiGe layer on top of a Si layer on insulator; transforming the crystalline Si layer and the lower portion of the crystalline relaxed SiGe layer into an amorphous material state by ion implantation; and re-crystallizing the amorphous material from the crystalline top portion of the SiGe layer. The larger lattice constant of the SiGe seed layer forces a tensile strain in the Si layer.

Inventors:
コーエン、ガイ、エム
クリスチャンセン、シルク、エイチ
Application Number:
JP2004565169A
Publication Date:
August 02, 2007
Filing Date:
December 02, 2003
Export Citation:
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Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L21/20; H01L21/02; H01L21/762; H01L27/12
Domestic Patent References:
JPH05259075A1993-10-08
JP2002110832A2002-04-12
JP2004047978A2004-02-12
JPH06112491A1994-04-22
JPH05259075A1993-10-08
JP2002110832A2002-04-12
JP2004047978A2004-02-12
JPH06112491A1994-04-22
Foreign References:
Other References:
JPN5005013699, AUBERTON−HERVE A J, ELECTRON DEVICES MEETING, 1996., INTERNATIONAL, 19961208, P3−10, US, IEEE
JPN5005013700, RIM K, COMPOUND SEMICONDUCTORS 1999. PROCEEDINGS OF THE 26TH INTERNATIONAL SYMPOSIUM 以下備考, 19990822, N166, P281−286, GB, IOP
Attorney, Agent or Firm:
坂口 博
市位 嘉宏
上野 剛史