Title:
MANUFACTURING METHOD OF LAMINATION MEMBER
Document Type and Number:
Japanese Patent JP2018174280
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a lamination member capable of preventing a semiconductor chip from coming into contact with an external lead-out terminal, and the like, without increasing the number of components.SOLUTION: A lamination member of three layer structure includes an upper high heat conduction layer where a mounting region to which the electrode of a semiconductor chip is joined, and the peripheral region of the mounting region are formed on the upper surface, a lower high heat conduction layer where a junction region to be joined to the heat slinger and the peripheral region of the junction region are formed on the lower surface, and an intermediate low thermal expansion coefficient layer provided between the upper and lower high heat conduction layers. In the plan view, the lamination member is larger than the semiconductor chip, height position of the peripheral region exists at a prescribed distance below the height position of the peripheral region, and height position of the peripheral region of the junction region exists at a prescribed distance above the height position of the junction region.SELECTED DRAWING: Figure 1
More Like This:
Inventors:
INAMI KAZUNORI
MARUYAMA TAKAHIRO
MARUYAMA TAKAHIRO
Application Number:
JP2017072938A
Publication Date:
November 08, 2018
Filing Date:
March 31, 2017
Export Citation:
Assignee:
SANSHA ELECTRIC MFG CO LTD
International Classes:
H01L23/36
Domestic Patent References:
| JP2010103311A | 2010-05-06 | |||
| JP2009065144A | 2009-03-26 | |||
| JP2008041708A | 2008-02-21 | |||
| JP2015191958A | 2015-11-02 | |||
| JPS5315782A | 1978-02-14 | |||
| JPH0778907A | 1995-03-20 | |||
| JPH0685109A | 1994-03-25 | |||
| JPS3818766B1 |
Attorney, Agent or Firm:
Kazuhiro Kiyohara