Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2585602
Kind Code:
B2
Abstract:
A bipolar type RAM having latches which accept and hold address signals, input write data and a write enable signal supplied from outside of the corresponding RAM chip, in accordance with strobe signals, and a timing generator circuit which forms the strobe signals and a write pulse required for a write operation and satisfying predetermined timing conditions, on the basis of a chip select signal supplied from outside.
Inventors:
USAMI MASAMI
AKIMOTO KAZUYASU
UCHAMA TAKEO
IWABUCHI MASATO
AKIMOTO KAZUYASU
UCHAMA TAKEO
IWABUCHI MASATO
Application Number:
JP14306387A
Publication Date:
February 26, 1997
Filing Date:
June 10, 1987
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11C7/22; G11C11/414; G11C11/416; (IPC1-7): G11C11/414
Domestic Patent References:
| JP5817593A | ||||
| JP60170090A | ||||
| JP60242583A | ||||
| JP61170992A |
Attorney, Agent or Firm:
Tomio Ohinata