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Title:
【発明の名称】集積回路を電気的に試験する方法および装置
Document Type and Number:
Japanese Patent JP2673888
Kind Code:
B2
Abstract:
PURPOSE: To thoroughly test an integrated circuit chip in a small area without requiring any expensive equipment by constituting a multidimensional array of probe lines and sense lines having electric switches at the intersections of the probe lines with the sense lines. CONSTITUTION: In part of a large-sized integrated circuit containing three probe lines Pn , Pn+1 , and Pn+2 and three sense lines Sm , Sm+1 , and Sm+2 , for example, an H signal on the probe line Pn allows a MOSFET switch controlled by Pn to conduct and signals at the output terminals of an AND gate, a NOR gate, and a NAND gate are respectively sent to the sense lines Sn Sn+1 and Sn+2 . When the probe lines Pn , Pn+1 , and Pn+2 are actuated at once, therefore, 9 signals at the intersections of the probe lines with the sense lines Sm , Sm+1 , and Sm+2 can be measured with the sense lines. Then the integrated circuit is tested by using different input signal pattern groups. The above-mentioned process is repeated until the integrated circuit is thoroughly tested under all input signal patterns required for confirming the proper functioning of the integrated circuit.

Inventors:
Tatsshire Earl Ziwara
Application Number:
JP264588A
Publication Date:
November 05, 1997
Filing Date:
January 11, 1988
Export Citation:
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Assignee:
Crosscheck Technology Incorporated
International Classes:
G01R31/28; H01L21/66; H01L21/822; H01L27/04; G01R31/317; (IPC1-7): H01L21/66; G01R31/317; H01L21/822; H01L27/04
Domestic Patent References:
JP61237521A
JP6142934A
JP62119955A
JP62259457A
JP5487142A
JP58186850A
Attorney, Agent or Firm:
Masaki Yamakawa (2 outside)



 
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