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Document Type and Number:
Japanese Patent JP2690007
Kind Code:
An extremely lightweight, interconnected array of semiconductor devices, such as solar cells, is formed from a large continuous area of semiconductor material (3, 23, 43, 83, 123) disposed on an unconventonally thin, electrically conducting stubstrate (1, 21, 41, 81, 121). The interconnections are formed by removing portions of the substrate to form substrate islands (13, 35, 55, 95, 141, 163, 183) underlying a layer of semiconductor material which underlies a transparent conductive oxide (5, 25, 45, 83, 125, 179). The oxide layer may likewise be formed into mutually isolated islands (7, 29, 47, 89, 131, 181) that overlay the areas between the substrate islands. Individual units or cells so formed may be interconnected by depositing a conducting material on, alongside and at least partially between islands of oxide and/or semiconductor, by depositing a metal grid (27) on the oxide layer and burning conducting paths (31) to the substrate islands, or by piercing the layers and disposing a conducting material in the holes (133) pierced. The unconventionally thin substrate may be a sheet of electroformel nickel or other thin metal or may be an initially thick substrate that is thinned by chemical etching after other array processing steps are completed. To maximize the output power-to-weight ratio of a solar cell array, the conventional substrate (159, 171) may be removed entirely. In that process, a dissimilar layer (161, 173), such as a back reflector, is deposited on a support, such as a conventional substrate, before the semiconductor material (23, 177) is deposited. After all other processing, the support (159, 171) is removed by chemical etching to produce a substrateless array of devices. Typically, the array is encapsulated by a protective glass or polymer film. An encapsulant (33) is preferably applied to the exposed surface of the semiconductor material to protect it while the substrate is being thinned or removed. Subsequently, an encapsulant (37) is applied to the rear of substrate side of the array. An insulating layer (173) may be interposed between the support (171) and semiconductor layer (177) and act to encapsulate the rear of a substrateless array when the support is etched away to produce an ultimate power-to-weight ratio array.

Yoo Jiff Jei Hanak
Application Number:
Publication Date:
December 10, 1997
Filing Date:
January 30, 1986
Export Citation:
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Energy Conversion Devices Incorporated
Canon Inc
International Classes:
H01L31/04; H01L27/142; H01L31/0392; H01L31/042; H01L31/20; (IPC1-7): H01L31/04; H01L31/042
Domestic Patent References:
Attorney, Agent or Firm:
Yoshikazu Tani (1 person outside)