Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
【発明の名称】ICコンデンサの製造方法及び半導体ICデバイス及びDRAMメモリセル
Document Type and Number:
Japanese Patent JP2798300
Kind Code:
B2
Abstract:
A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. First the bottom polycrystalline silicon plate layer (26)is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer(30,50). Following another isolation step, the polycrystalline silicon top plate layer(62)is then formed and connected to the bottom plate layer. The storage electrode employs a buffer polysilicon layer (30) and contacts the active region via an etched hole using sidespacer insulation(48). Sidespacers (60) are also used to isolate the outer edges of the storage electrode.

Inventors:
ツィウ・チウ・チャン
フランク・ランドルフ・ブライアント
Application Number:
JP31444990A
Publication Date:
September 17, 1998
Filing Date:
November 21, 1990
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
エスジーエス‐トムソン・マイクロエレクトロニクス・インコーポレイテッド
International Classes:
H01L27/04; H01L21/02; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/822; H01L21/8242; H01L27/04
Domestic Patent References:
JP335554A
JP1154551A
JP2263467A
JP2295160A
JP2305470A
JP294561A
Attorney, Agent or Firm:
曾我 道照 (外2名)