Title:
【発明の名称】半導体メモリ試験装置
Document Type and Number:
Japanese Patent JP2842923
Kind Code:
B2
Abstract:
In an analysis for saving failures of a semiconductor memory, a comparison is made between data written into each cell of the semiconductor memory and data read out therefrom, and in the case of a disagreement, a "1" is written by a read modify write operation into a failure analysis memory (17) at a memory cell specified by column and row addresses corresponding to the respective cell of the semiconductor memory and data read out of the memory cell of the failure analysis memory is provided as in inhibit signal to a gate (22). A disagreement signal is applied as a write command via the gate to column and row address fail count memories (23, 24) and, at the same time, it is counted by a fail counter (25). The number of defective cells on each column address line, the number of defective cells on each row address line and the total number of defective cells are obtained in the column address fail count memory, the row address fail count memory and the fail counter. The number of defective cells is read out of each address of the column address fail count memory and is compared by a comparator with the number of row spare lines of the memory under test. When the former is greater than the latter, the column address of the memory under test is decided as a failing address line and the compared output is counted by a failing address line counter, and at the same time, the column address of the failing address line is written as data into a failing address memory, using the count value of the failing address line counter as an address for the write. The row address is sequentially changed, beginning with a 0, at each column address decided as failing, and each time a "1" is read out of the failure analysis memory, the contents of the corresponding addresses of the column and row address fail count memories are each rewritten by subtracting a 1 therefrom by a subtractor, and at the same time, the content of the fail counter is decremented by one.
Inventors:
FUJISAKI KENICHI
OKINO NOBORU
OKINO NOBORU
Application Number:
JP6909390A
Publication Date:
January 06, 1999
Filing Date:
March 19, 1990
Export Citation:
Assignee:
ADOBANTESUTO KK
International Classes:
G01R31/28; G11C29/00; G11C29/40; G11C29/44; (IPC1-7): G01R31/28; G11C29/00
Domestic Patent References:
| JP62276475A | ||||
| JP60209999A | ||||
| JP585681A | ||||
| JP63127499A |
Attorney, Agent or Firm:
Kusano Takashi