Title:
【発明の名称】信号レベル変換回路
Document Type and Number:
Japanese Patent JP2871551
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a signal level conversion circuit consisting of an inverter circuit and a level conversion circuit which can increase the signal level conversion speed and also can reduce the power consumption by eliminating a long time when the potential of an output signal line shifts after the potential of an input signal line shifts and also eliminating occurrence of a through current. SOLUTION: An inverter circuit (transistors TR P1 and N1) outputs the potential level of a 2nd power line 102 when the input signal of an input signal line 105 is equal to the potential of a 3rd power line 103 and then outputs the potential level of a 1st internal power line 107 when the input signal of the line 105 is equal to the potential of the line 103 respectively. Then a switch circuit (TR P2, P3, P4 and N5) outputs the potential of the line 103 to the line 107 when the input signal of the line 105 is equal to the potential of the power line 103 and then outputs the potential of a 1st power line 101 to the line 107 when the input signal of the line 105 is equal to the potential of the line 102 respectively.
Inventors:
MIZUNO MASAYUKI
Application Number:
JP25554795A
Publication Date:
March 17, 1999
Filing Date:
September 07, 1995
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H03K17/16; H03K5/00; H03K19/0185; H03K19/0948; (IPC1-7): H03K19/0185
Attorney, Agent or Firm:
Suzuki Akio