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Title:
【発明の名称】電源モニタ回路
Document Type and Number:
Japanese Patent JP2885177
Kind Code:
B2
Abstract:
In a buffering circuit, a CMOS inverter is connected between a node and a ground terminal. A source-follower-type MOS transistor is connected between a power supply terminal and the node, and a approximately definite voltage is applied to a gate of the source-follower-type MOS transistor. A MOS transistor is connected in parallel to the source-follower-type MOS transistor, and an inverted signal of an output signal of the CMOS inverter is applied to a gate of the MOS transistor.

Inventors:
OOWADA MASAKATSU
Application Number:
JP9308696A
Publication Date:
April 19, 1999
Filing Date:
March 22, 1996
Export Citation:
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Assignee:
NIPPON DENKI KK
International Classes:
G01R19/165; H03K5/08; H03K5/24; H03K19/00; H03K19/003; H03K19/0948; (IPC1-7): G01R19/165; H03K19/00; H03K19/003; H03K19/0948
Domestic Patent References:
JP63164526A
JP6291640A
JP720165A
JP5672522A
JP63261168A
JP5326175A
JP1156674A
JP4175666A
JP62194732A
JP3127512A
Attorney, Agent or Firm:
Asato Kato