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Patent Searching and Data


Title:
セル配置方法
Document Type and Number:
Japanese Patent JP3076330
Kind Code:
B1
Abstract:
PROBLEM TO BE SOLVED: To prevent arrangement with excessive substrate contacts to reduce the chip area and suppress the cost. SOLUTION: Related to a standard cell arrangement process P, based on the information provided by a cell arranged in an array in a standard cell arrangement region, and the width of array in the standard cell arrangement region as well as the data for the interval with which at least one substrate contact must be arranged, the number of substrate contacts added to the array in the standard cell arrangement region is acquired. A region where a substrate contact can be added is assured for arrangement of a cell, and cell's movement and arrangement with the substrate contact are performed so that at least one substrate contact is present in an interval L.

Inventors:
石川 博嗣
Application Number:
JP7359799A
Publication Date:
August 14, 2000
Filing Date:
March 18, 1999
Export Citation:
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Assignee:
日本電気アイシーマイコンシステム株式会社
International Classes:
H01L21/822; G06F17/50; H01L21/82; H01L27/04; (IPC1-7): H01L21/82; G06F17/50; H01L21/822; H01L27/04
Attorney, Agent or Firm:
菅野 中