【発明の名称】2個以上の集積回路を一つの集積回路へ併合する方法

Japanese Patent JP3244270

B2

The technique takes advantage of the current ability to increase the density of electronic circuit elements on an integrated circuit chip by combining onto a single chip all of the circuit elements of two or more separate circuits, even when the masks of the separate circuits have been laid out with one or more different design rules, and then connect them to operate together. A mask layout database of one of the circuits at a time is globally changed, with the use of a standard computer software package, to conform it to the design rules of the mask layout database of another circuit, either before or after the circuit databases are combined into a single database.

JPH0313877	METHOD FOR TESTING LIFE OF WIRING
JPS63502312	[Title of the Invention] Double layer photoresist processing for Well self-alignment and ion implantation masking
JP6509323	Electromigration, inrush current effect, IR voltage drop, and jitter reduction through metal line and via matrix insertion

Nilai, Kumar

JP29871790A

January 07, 2002

November 02, 1990

Click for automatic bibliography generation  

Zilog, Inc.

H01L21/82; G06F17/50; (IPC1-7): H01L21/82

JP6115348A
JP1147841A

Hisashi Inokuchi

Previous Patent: Hook structure and Velcro fastener

Next Patent: サリチル単位から誘導された新規二芳香族化合物、その製法ならびにヒト�...