Title:
SDメモリカードホストコントローラ及びクロック制御方法
Document Type and Number:
Japanese Patent JP3552213
Kind Code:
B2
Abstract:
An SD memory card host controller supplies a clock (SDCLK) to an SD memory card and issues a read command (SDCMD). After that, the host controller stops supplying the clock (SDCLK) to the SD memory card during latency of read data from receipt of a response to the read command from the SD memory card to readout of data. The host controller resumes supplying the clock (SDCLK) immediately before a data cycle starts. Power savings can thus be achieved by controlling the clock to be supplied to the SD memory card.
Inventors:
Ken Takamiya
Yasunori Maki
Yasunori Maki
Application Number:
JP2001264356A
Publication Date:
August 11, 2004
Filing Date:
August 31, 2001
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06K17/00; G06F1/32; G06F3/08; G06F12/00; (IPC1-7): G06K17/00; G06F12/00
Domestic Patent References:
| JP2001014441A | ||||
| JP2001184304A | ||||
| JP9097128A | ||||
| JP8147161A | ||||
| JP4222009A | ||||
| JP460859A |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai