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Patent Searching and Data


Title:
半導体回路装置
Document Type and Number:
Japanese Patent JP3615126
Kind Code:
B2
Abstract:
In a semiconductor chip are arranged power pads, ground pads and signal pads. A ground line is provided which is formed as one in the vicinity of the chip and branches off at some distance from the chip. Signal lines and power lines are each formed over one of the branched ground lines. The signal lines and the power lines are extended radially together with the underlying ground lines. Each of the signal lines and the power lines are extended together with the corresponding ground line to form a stacked pair line.

Inventors:
Kanji Otsuka
Yasushi Usami
Application Number:
JP2000209861A
Publication Date:
January 26, 2005
Filing Date:
July 11, 2000
Export Citation:
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Assignee:
大塚 寛治
宇佐美 保
株式会社東芝
沖電気工業株式会社
三洋電機株式会社
シャープ株式会社
ソニー株式会社
日本電気株式会社
株式会社ルネサステクノロジ
富士通株式会社
松下電器産業株式会社
ローム株式会社
International Classes:
H01L21/822; H01L21/60; H01L21/82; H01L23/66; H01L27/04; H01P3/08; H04L25/02; (IPC1-7): H01L21/822; H01L21/82; H01L27/04; H01P3/08
Domestic Patent References:
JP11284126A
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Atsushi Tsuboi
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Yamato Tsutsui