Title:
ビデオデータデコーダのアーキテクチャ
Document Type and Number:
Japanese Patent JP3615241
Kind Code:
B2
Abstract:
A video data processing system (10) has a first substrate (12) and a second substrate (14). A system decoder (16), input buffer (18) and parser (20) are formed on first substrate (12). The parser (20) retrieves video data information from an input data stream and feeds coefficients through a dequantization unit (22) and a transformation unit (24). In addition, motion vector information is output from the parser (20). The second substrate (14) comprises a plurality of picture frame buffers 38, 40 and 44. The frame buffers 38, 40 and 44 are used to store decoded video information. Motion compensation modules 26a and 26b are used to perform predicted calculations on the information received from the video data stream as well as other images that have already been decoded. A raster scan output buffer (46) is used to output the decoded video information.
Inventors:
Hashimoto Seishi
Frank El Racco Senior
Frank El Racco Senior
Application Number:
JP19039094A
Publication Date:
February 02, 2005
Filing Date:
August 12, 1994
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
G06T9/00; H04N5/92; H04N5/937; H04N7/26; H04N7/32; H04N7/36; H04N7/50; (IPC1-7): H04N7/32
Domestic Patent References:
| JP5137131A | ||||
| JP6119440A | ||||
| JP5260462A |
Attorney, Agent or Firm:
Minoru Nakamura
Fumiaki Otsuka
Shishido Kaichi
Hideto Takeuchi
Toshio Imajo
Nobuo Ogawa
Village shrine Atsuo
Fumiaki Otsuka
Shishido Kaichi
Hideto Takeuchi
Toshio Imajo
Nobuo Ogawa
Village shrine Atsuo