Title:
半導体メモリ
Document Type and Number:
Japanese Patent JP3615561
Kind Code:
B2
Abstract:
There is described a semiconductor memory comprising a matrix of lines and columns of memory cells, wherein the columns (BL) are grouped together in sectors, each sector representing the portion of the matrix itself related to a data input/output line. Each sector is in turn divided into packets (1) of columns, and there are redundancy columns (BLR) suitable for replacing a matrix column (BL) containing defective memory cells. Each of the redundancy columns (BLR) is included in a respective packet (1). The memory also comprises control circuits (5,6,7) to execute the abovementioned replacement.
Inventors:
Marco Olivo
Ruigi Pascucci
Ruigi Pascucci
Application Number:
JP5878794A
Publication Date:
February 02, 2005
Filing Date:
March 29, 1994
Export Citation:
Assignee:
STMicroelectronics S.r.l.
International Classes:
G11C29/00; G11C11/00; G11C29/04; (IPC1-7): G11C29/00
Domestic Patent References:
| JP5074191A | ||||
| JP59144098A | ||||
| JP4103099A | ||||
| JP63308797A | ||||
| JP4146596A |
Foreign References:
| EP0472209A1 |
Attorney, Agent or Firm:
Kosaku Sugimura
Yasunori Sato
Norita Tomita
Umemoto Masao
Takashi Nihei
Yasunori Sato
Norita Tomita
Umemoto Masao
Takashi Nihei