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Title:
最適化コンパイラ、コンパイラプログラム、及び記録媒体
Document Type and Number:
Japanese Patent JP4042972
Kind Code:
B2
Abstract:
Provides methods, apparatus and systems for an optimizing compiler which optimizes load instructions to read out data from a memory in an object program targeted for optimization. In an example embodiment, an optimizing compiler includes partial redundancy eliminating means for performing partial redundancy elimination on load instructions to read out variable data from the memory so that spilling does not take place when the variables are assigned to the registers; backward register detecting means for detecting free registers, which are not assigned to any variable, along execution paths traced in reverse order of execution, starting backward from use instructions to use data read out by the load instructions and extending to the load instructions; and free register assigning means for assigning the free registers detected by the backward register detecting means to target variables to be read out by the load instructions.

Inventors:
川人 基弘
Application Number:
JP2003339666A
Publication Date:
February 06, 2008
Filing Date:
September 30, 2003
Export Citation:
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Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G06F9/45
Domestic Patent References:
JP2004227025A
JP200578474A
Foreign References:
Attorney, Agent or Firm:
坂口 博
市位 嘉宏
上野 剛史