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Patent Searching and Data


Title:
半導体メモリ装置の制御方法
Document Type and Number:
Japanese Patent JP4187197
Kind Code:
B2
Abstract:
A semiconductor memory device (2) comprises a memory cell formed of a nonvolatile resistance variable memory device (23B) in which a resistance value is variable according to the application of electrical stress, and a selection transistor (23A); and word-line-voltage feeding means that feeds a word line voltage to a word line to be coupled to the memory cell. When executing a program operation for the memory cell (23) and a verify operation for verifying a program state of the memory cell (23), the word-line-voltage feeding means (22) feeds the word line voltage of the same voltage level to the word line to be coupled to the memory cell selected as a program target for two operations set as mutually related front and rear steps, namely, a program operation to be executed for the memory cell and a verify operation to be executed to verify a program state of the memory cell (23).

Inventors:
Koji Hamaguchi
Application Number:
JP2002324329A
Publication Date:
November 26, 2008
Filing Date:
November 07, 2002
Export Citation:
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Assignee:
Sharp Corporation
International Classes:
G11C13/00; G11C16/02; G11C11/56; G11C16/04; G11C16/06; G11C16/34
Domestic Patent References:
JP2116092A
JP2000149581A
JP2002184190A
JP8330944A
Foreign References:
US6473332
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Takeshi Oshio