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Patent Searching and Data

Document Type and Number:
Japanese Patent JP4190238
Kind Code:
Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row select signal. Corresponding to a row of memory cells, there is provided a word line connecting to memory cells on corresponding row and transmitting the row select signal, and a word line shunting line electrically connected at predetermined intervals to each word line. Moreover, corresponding to a row of dummy cells and a column of dummy cells, there is provided substrate shunt lines electrically connected to the substrate region. The voltage distribution in the substrate region is eliminated to achieve stable operating characteristics of the memory cell transistor. In addition, a word line is driven at high speed by a word line shunt structure.

大石 司
Application Number:
Publication Date:
December 03, 2008
Filing Date:
September 13, 2002
Export Citation:
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International Classes:
G11C13/00; G11C5/02; G11C7/14; G11C16/02; H01L27/10; H01L27/105; H01L27/24
Domestic Patent References:
Foreign References:
Attorney, Agent or Firm:
深見 久郎
森田 俊雄
仲村 義平
堀井 豊
野田 久登
酒井 將行