Title:
モジュール制御回路を備えたメモリモジュール
Document Type and Number:
Japanese Patent JP4272732
Kind Code:
B2
Abstract:
A memory module having a module control circuit which is capable of decreasing an operational current by configuring a 1BANK 4Mx64 module using 16M DRAMs (1K Refreshx16) and reducing the number of operational devices. The module control circuit decodes externally inputted eleventh and twelfth address signals and outputs control signals in accordance with one of a plurality of column address strobe signals and a row address strobe signal, and a plurality of DRAMs in a memory unit are selected by the control signals from the module control circuit and are parallely connected for performing a data write and read operation in accordance with externally inputted first through tenth address signals, a write enable signal, an output enable signal, and the column address strobe signals.
Inventors:
Park
Golden rule
Golden rule
Application Number:
JP36863798A
Publication Date:
June 03, 2009
Filing Date:
December 25, 1998
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G06F12/06; G11C11/401; G06F12/00; G06F12/02; G11C8/10; G11C11/34
Domestic Patent References:
| JP8044622A | ||||
| JP9265774A | ||||
| JP8006848A | ||||
| JP6295262A | ||||
| JP1260690A | ||||
| JP9231127A | ||||
| JP10188554A |
Attorney, Agent or Firm:
Hajime Tsukuni
Mutsuo Watanabe
Fumio Shinoda
Tomoko Saeki
Mutsuo Watanabe
Fumio Shinoda
Tomoko Saeki