半導体装置およびその作製方法 - Semiconductor Energy Laboratory Co., Ltd.

Title:

半導体装置およびその作製方法

Document Type and Number:

Japanese Patent JP4339000

Kind Code:

B2

Abstract:

To provide the structure of a semiconductor device realizing low power consumption even if a large screen is applied, and a method of manufacturing the same.

An insulating layer 101 is formed. Buried wiring (Cu, Au, Ag, Ni, chromium, palladium, rhodium, tin, lead, or their alloy or the like) 104a, 104b are formed in the insulating layer. In addition, the surface of the insulating layer is flattened, and a metal protective film (Ti, TiN, Ta, TaN or the like) is formed on an exposed portion. The low resistance of the wiring is achieved by using the buried wiring for part of various wiring (gate wiring, source wiring, power supply wiring, common wiring, or the like) of a light emitting device or a liquid crystal display device.

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Inventors:

Toru Takayama
Shunpei Yamazaki

Application Number:

JP2003084808A

Publication Date:

October 07, 2009

Filing Date:

March 26, 2003

Export Citation:

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Assignee:

Semiconductor Energy Laboratory Co., Ltd.

International Classes:

G02B5/20; G09F9/30; G02F1/1343; H01L21/3205; H01L23/52; H01L29/786; H01L51/50; H05B33/12; H05B33/14

Domestic Patent References:

JP7020489A
JP10209463A
JP5061067A
JP2001249362A
JP11026394A

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