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Document Type and Number:
Japanese Patent JP4340646
Kind Code:

To provide a communication processing circuit capable of transferring a packet which must be transferred to a CPU out of received packets to the CPU without discarding it.

The communication processing circuit is provided with a plurality of queues 73-1 to 73-N. A frame analyzer 31 and a frame search 41 detect frame information of a frame as a target to be input into the CPU from among the frames to be received. A queue input 60 selects the queues 73-1 to 73-N having priorities corresponding to information indicating a factor by which the frame information detected by a detecting means is a target input into the central processing circuit, and generates job information based on this frame information and inputs the generated information into the selected queues 73-1 to 73-N. A queue outputting section 80 orderly reads the job information from the plurality of queues 73-1 to 73-N in conformity with a predetermined queue reading regulation, and inputs the frame information corresponding to the read job information into the CPU.


Kenji Kawai
Yoshikuni Nishida
Shuichi Chaki
Keiichi Koike
Katsuichi Oyama
Tetsuo Hayashi
Hiroyuki Nouchi
Application Number:
Publication Date:
October 07, 2009
Filing Date:
October 26, 2005
Export Citation:
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Nippon Telegraph and Telephone Corporation
NTT Electronics Corporation
International Classes:
H04L12/701; H04L12/861; H04L12/931
Domestic Patent References:
Attorney, Agent or Firm:
Yuichi Negishi
Yasushi Motoyama