Title:
単一チップシステム及びこのシステムのテスト/デバッグ方法
Document Type and Number:
Japanese Patent JP4422427
Kind Code:
B2
Abstract:
A system on chip and method of testing and/or debugging the same, where the system on chip includes a plurality of circuits and a control circuit for receiving a serial-parallel mode control signal and at least one selection signal externally input from one or more of a plurality of pins and outputting an output signal depending on values of the serial-parallel mode control signal and the at least one selection signal.
Inventors:
South Korea
Application Number:
JP2003109502A
Publication Date:
February 24, 2010
Filing Date:
April 14, 2003
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
G01R31/28; G01R31/317; G06F11/22; G01R31/3185; G11C29/00
Domestic Patent References:
| JP7182305A | ||||
| JP2004500712A |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro