To provide a manufacturing process that employs a drop discharge method suitable for a large-sized substrate in terms of volume production considering that a signal delay problem due to the resistance of wiring will possibly become prominent when manufacturing a semiconductor apparatus having a large-area display.
The process includes steps of, forming a foundation layer 11 (or to pre-treat for the foundation layer) beforehand on a substrate that improves its adhesiveness, and forming a mask of a desired pattern shape, which is used to form a desirable concave portion after forming an insulation film. The drop discharge method is used to fill a metal material into the concave portion that has a side wall composed of a mask 13 and the insulation film, thus forming embedded wiring (a gate electrode 15, a power line, guided wiring, and the like). After the mask 13 is removed, planarizing process, such as pressing and CMP, is performed to planarize the element.
COPYRIGHT: (C)2005,JPO&NCIPI
Shunpei Yamazaki
Shinji Maekawa
Osamu Nakamura
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