Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
メインマイクロプロセッサと、バス送受信ユニットに対するプロセッサインタフェースとを有する制御装置
Document Type and Number:
Japanese Patent JP4741750
Kind Code:
B2
Abstract:
The control device has a main microprocessor coupled to a processor interface for connection to a bus transmission/reception device having a transmission memory, a reception memory and a bus controller. The data held in the transmission memory and/or the reception memory is provided with an invalidity identification after each read-out and/or write-in operation before new data is delivered by the microprocessor or fed to the microprocessor. An Independent claim for a method for preventing transmission of invalid data, via a control device is also included.

Inventors:
ヨアヒム フレシュル
ヨーゼフ クラマー
アントン シェドル
Application Number:
JP2001183696A
Publication Date:
August 10, 2011
Filing Date:
June 18, 2001
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
BAYERISCHE MOTOREN WERKE AKTIENGESELLSCHAFT
International Classes:
G06F12/16; G06F13/00; G05B19/042
Domestic Patent References:
JP63124161A
JP3268153A
Attorney, Agent or Firm:
藤田 アキラ



 
Previous Patent: 脱着式ノズル

Next Patent: JPS4741751