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Document Type and Number:
Japanese Patent JP4998699
Kind Code:
The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B. The controller controls in such way that the core B can receive only the data arriving prior to the setup of the clock signal clkB. The controller stores the history on a communication status between cores.

Mitsufumi Shibayama
Koichi Nose
Mizuno Masayuki
Application Number:
Publication Date:
August 15, 2012
Filing Date:
September 16, 2005
Export Citation:
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International Classes:
H04L7/00; G06F1/12; G06F13/42
Domestic Patent References:
Attorney, Agent or Firm:
Katsumi Utaka