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Title:
メモリシステム
Document Type and Number:
Japanese Patent JP5010505
Kind Code:
B2
Abstract:
A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.

Inventors:
Junji Yano
Hidenori Matsuzaki
Kosuke Hatsuda
Toshikatsu Hinoda
Application Number:
JP2008051470A
Publication Date:
August 29, 2012
Filing Date:
March 01, 2008
Export Citation:
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Assignee:
Toshiba Corporation
International Classes:
G06F12/02; G06F12/00; G06F12/06; G06F12/16; G11C16/02
Domestic Patent References:
JP2007334413A
JP2003228513A
JP2006504201A
Foreign References:
WO2002046929A1
Attorney, Agent or Firm:
Hiroaki Sakai



 
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