Title:
電子デバイス製造プロセス
Document Type and Number:
Japanese Patent JP5074048
Kind Code:
B2
Abstract:
A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
Inventors:
William s won
Scott Jay Lynn
Michael El Chabinik
Beverly Russo
Rene Airu
Scott Jay Lynn
Michael El Chabinik
Beverly Russo
Rene Airu
Application Number:
JP2007011715A
Publication Date:
November 14, 2012
Filing Date:
January 22, 2007
Export Citation:
Assignee:
Palo Alto Research Center Incorporated
International Classes:
G02B5/20; G03F1/92
Domestic Patent References:
| JP11160862A | ||||
| JP10039126A | ||||
| JP2005183994A | ||||
| JP2002348684A | ||||
| JP2005535120A |
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida
Jun Ishida