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Title:
ディープパワーダウンモード制御回路
Document Type and Number:
Japanese Patent JP5100218
Kind Code:
B2
Abstract:
A deep power down mode control circuit is provided. The deep power down mode control circuit includes a deep power down signal generator for outputting a deep power down signal in response to a burst command signal and a clock enable signal, and a deep power down delay controller for delaying the deep power down signal for a predetermined delay time, and outputting the delayed signal.

Inventors:
Autumn Shinho
Application Number:
JP2007168036A
Publication Date:
December 19, 2012
Filing Date:
June 26, 2007
Export Citation:
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Assignee:
SK hynix Inc.
International Classes:
G11C11/401; G11C11/4076
Domestic Patent References:
JP2003304146A
JP2002358781A
JP2004039205A
Attorney, Agent or Firm:
Yasuo Ishikawa
Takahiro Imai
Kazuyuki Oku