Title:
プログラム可能高速入出力インターフェース
Document Type and Number:
Japanese Patent JP5268195
Kind Code:
B2
Abstract:
Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
Inventors:
Bonnie I One
Chiakan Sun
Joseph fan
Kai Nguyen
Philip Pan
Chiakan Sun
Joseph fan
Kai Nguyen
Philip Pan
Application Number:
JP2010001545A
Publication Date:
August 21, 2013
Filing Date:
January 06, 2010
Export Citation:
Assignee:
Altera Corporation
International Classes:
G06F3/00; H03K19/173; G06F13/38; H01L21/82; H03K19/0175; H03K19/177; H01L21/822; H01L27/04
Domestic Patent References:
| JP9006592A | ||||
| JP2001167575A | ||||
| JP8222704A | ||||
| JP4192809A |
Foreign References:
| US6236231 |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Natsuki Morishita
Natsuki Morishita