Title:
DLL回路及びその制御方法
Document Type and Number:
Japanese Patent JP5451012
Kind Code:
B2
Abstract:
A DLL (delay locked loop) circuit includes a first variable delay circuit, a pair of second variable delay circuits and a first synthesis circuit. The first variable delay circuit outputs signals of different delayed time values from each of first and second clock transitions. The pair of second variable delay circuits receive the signals from the first variable delay circuit, and the first synthesis circuit synthesizes output signals of the pair of second variable delay circuits to output the resulting synthesized signal. Each of the pair of second variable delay circuits includes a pair one-shot pulse generating circuits that generate one-shot pulses from the signals from the first variable delay circuit, a pair latch circuits, and a second synthesis circuit. The second synthesis circuit receives the set outputs of the latch circuits to output a signal which is a synthesis at a preset synthesis ratio.
Inventors:
Tsuneo Abe
Application Number:
JP2008227324A
Publication Date:
March 26, 2014
Filing Date:
September 04, 2008
Export Citation:
Assignee:
PS4 Luxco S.a.r.l.
International Classes:
H03K5/04; G11C11/407; G11C11/4076; H03K3/033; H03K5/13; H03L7/081
Domestic Patent References:
| JP2006129180A | ||||
| JP2007228044A | ||||
| JP200899002A | ||||
| JP200551673A | ||||
| JP200156723A |
Attorney, Agent or Firm:
Kato Asamichi
Kiuchi Uchida
Mitsuru Aoki
Kiuchi Uchida
Mitsuru Aoki