Title:
縮退故障を有するメモリセル内にビットを記憶するための技術
Document Type and Number:
Japanese Patent JP5722420
Kind Code:
B2
Abstract:
A data storage system includes a memory circuit comprising memory cells and a control circuit. The control circuit generates a first set of redundant bits indicating bit positions of the memory cells having stuck-at faults in response to a first write operation if a first rate of the stuck-at faults in the memory cells is greater than a first threshold. The control circuit is operable to encode data bits to generate encoded data bits and a second set of redundant bits that indicate a transformation performed on the data bits to generate the encoded data bits in response to a second write operation if a second rate of stuck-at faults in the memory cells is greater than a second threshold. The encoded data bits stored in the memory cells having the stuck-at faults match digital values of corresponding ones of the stuck-at faults.
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Inventors:
Cyril Guyote
Louise Franca-Neto
Robert Eugene Mathieu Skew
Zvonimir Bandic
Kimbo One
Louise Franca-Neto
Robert Eugene Mathieu Skew
Zvonimir Bandic
Kimbo One
Application Number:
JP2013256009A
Publication Date:
May 20, 2015
Filing Date:
December 11, 2013
Export Citation:
Assignee:
H.G. Esteneetherland Bee Buoy
International Classes:
G06F12/16; G11C13/00
Domestic Patent References:
| JP5646723B2 | ||||
| JP201478237A | ||||
| JP51087928A | ||||
| JP51137335A | ||||
| JP51138335A |
Foreign References:
| US20130124942 | ||||
| US20130124943 |
Attorney, Agent or Firm:
Haruka International Patent Office