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Title:
半導体集積装置
Document Type and Number:
Japanese Patent JP6657962
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor integrated device that can reduce the circuit scale.SOLUTION: A semiconductor integrated device 1 includes a magnification setting circuit 1a, a V-I conversion circuit 1b, and a frequency generation circuit 1c. The magnification setting circuit 1a includes a resistor group 1a-2 for determining the magnification of an oscillation frequency, and a transistor Tr1 that turns on with base current flowing due to an input voltage and outputs an emitter voltage Ve1 obtained by subtracting the base-emitter voltage from the input voltage, and outputs the voltage Vout obtained by amplifying the emitter voltage Ve1 via the resistor group 1a-2. The V-I conversion circuit 1b includes a transistor Tr2 for receiving the voltage Vout at the base, a transistor Tr3, a transistor Tr4 for determining the upper limit of the emitter voltage Ve2 of the transistor Tr3, and a resistor R3 for converting the emitter voltage Ve2 of the transistor Tr3 to current Iout, and converts the voltage Vout to the current Iout. The frequency generation circuit 1c charges a capacitor with current proportional to the current Iout to generate a clock signal ck of a predetermined frequency.SELECTED DRAWING: Figure 1

Inventors:
中込 謙司
Application Number:
JP2016000477A
Publication Date:
March 04, 2020
Filing Date:
January 05, 2016
Export Citation:
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Assignee:
富士電機株式会社
International Classes:
H03K4/502; H03K3/354
Domestic Patent References:
JP2013187716A
JP4048877A
JP2009171405A
JP52119047A
Attorney, Agent or Firm:
特許業務法人扶桑国際特許事務所