Title:
電子制御システム
Document Type and Number:
Japanese Patent JP6814858
Kind Code:
B2
Abstract:
To provide a semiconductor device with which it is possible to accurately detect presence/absence of a bridging fault of a resolver by using potential of an existing external terminal provided on a chip that forms a converter.SOLUTION: According to one embodiment, a semiconductor device comprises: external terminals S1 and S3 to which one and the other of a pair of voltage signals corresponding to a detection result of a resolver 11 are supplied via input resistors R1 and R3, respectively; an op-amp AP11 for amplifying a potential difference in the pair of voltage signals supplied to the external terminals S1 and S3; a feedback resistor R13 provided between the output terminal of the op-amp AP11 and one input terminal; switches SW1 and SW3 provided between the two input terminals of the op-amp AP11 and the external terminals S1 and S3, respectively; and a bridging fault detection circuit 102 for detecting whether or not a bridging fault has occurred in the resolver 11 on the basis of a voltage level of each of the external terminals S1 and S3 when the switches SW1 and SW3 are turned off.SELECTED DRAWING: Figure 1
Inventors:
Kazuaki Kurooka
Yasuo Morimoto
Funato
Yasuo Morimoto
Funato
Application Number:
JP2019169359A
Publication Date:
January 20, 2021
Filing Date:
September 18, 2019
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G01D5/244; G01D5/20
Domestic Patent References:
| JP2015059788A | ||||
| JP2005345189A | ||||
| JP2011127997A | ||||
| JP2015094718A | ||||
| JP2009162670A |
Foreign References:
| US7031031 | ||||
| CN101907962A |
Attorney, Agent or Firm:
Ken Ieiri