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Patent Searching and Data

Document Type and Number:
Japanese Patent JP7062409
Kind Code:
A self-test capable integrated circuit apparatus comprising a pattern generator (200), a results store (205) and testable logic (202, 204, 206). The testable logic (202, 204, 206) comprises a plurality of scan channels (202, 204), each of the channels (202, 204) being respectively coupled between the pattern generator (200) and the results store (205). A self-test controller (108) is arranged to supervise a self-test in respect of the testable logic (202, 204, 206) to generate self-test result data, the self-test result data being stored in the results store (205). A processing resource (206) is also coupled to the self-test controller(108) and coupled between the pattern generator (200) and the results store (205), the processing resource (206) being capable of evaluating the self-test result data stored in the results store (205). The testable logic (202, 204, 206) comprises the processing resource (206), which is arranged to cooperate with the self-test controller (118) so that the self-test is also in respect of the processing resource (206) and the processing resource (206) is able subsequent to the self-test to evaluate the self-test result data.

Fuki Yassine
Chegarak Georges
De Meij Eric
Proutino Luca
Sapienza Martina
Application Number:
Publication Date:
May 16, 2022
Filing Date:
November 08, 2017
Export Citation:
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u-blox AG
International Classes:
H01L21/822; G01R31/28; G06F11/22; G06F11/27; H01L27/04
Domestic Patent References:
Attorney, Agent or Firm:
Hiroyuki Nagai
Nakamura Yukitaka
Yasukazu Sato
Satoru Asakura
Takeshi Sekine
Hiroshi Yoshimoto