Document Type and Number:
Japanese Patent JPH01503786
Kind Code:
A
Abstract:
This connected-speech recognition system uses a two-level hierarchical system, in which the higher-level (master) processor and one or more lower-level units (slaves) process, respectively, the most probably word sequence within a permitted grammar network, and the likelihood of individual words with the grammar network. The lower-level processing performs dynamic programming involving vector and matrix calculation and comparison, and processing speed is improved by an integrated processing unit which has simultaneous access to the external data memory as well as to a high-speed internal microinstruction ROM. One of the aforementioned units can also provide for performing an additional internal test function. The structure features two internal data buses and internal memories for more commonly used data and addresses, for enabling high-speed microinstruction performance and external memory access. The external memory is divided into tables differing structurally but such as to be accessed in uniform manner by the internal addressing unit.
Application Number:
JP50167388A
Publication Date:
December 21, 1989
Filing Date:
February 10, 1988
Export Citation:
International Classes:
A61K31/415; A61K31/4184; A61K31/557; A61P1/04; C07C27/00; C07C29/143; C07C35/06; C07C45/00; C07C47/192; C07C51/00; C07C59/11; C07C59/353; C07C67/00; C07C69/67; C07C69/675; C07C69/716; C07C209/00; C07C209/26; C07C213/00; C07C227/00; C07C227/08; C07C239/00; C07C241/00; C07C243/20; C07C247/06; C07D209/54; C07C247/12; C07C247/14; C07C253/00; C07C255/31; C07D235/02; G10L15/00; G10L15/12; G10L15/14; (IPC1-7): A61K31/415; A61K31/557; C07C35/06; C07C43/315; C07C47/192; C07C59/11; C07C59/353; C07C69/67; C07C69/675; C07C69/716; C07C87/34; C07C91/14; C07C95/06; C07C97/065; C07C101/04; C07C101/18; C07C101/24; C07C102/00; C07C103/737; C07C109/02; C07C117/00; C07C121/42; C07C133/00; C07D209/54; C07D235/02