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Patent Searching and Data

Document Type and Number:
Japanese Patent JPH07112184
Kind Code:
A data transfer synchronization method and circuit allows data to be transferred between two synchronous systems running asynchronously with each other in a way that does not require the receiving system clock to be running twice as fast as the source system clock. Data is clocked into a first set of flip-flops by the clock signal of the source system. The source system clock signal is also used to toggle a toggle flip-flop. The receiving system clock signal is used to clock a first clock bit flip-flop coupled to detect the state of the toggle flip-flop. A delayed version of the receiving system clock signal is used to clock the output of the first set of flip-flops into a second set of flip-flops. The normal (undelayed) receiving system clock signal is used to clock the output of the second set of flip-flops into a third set of flip-flops. A data valid signal is generated when the third set of flip-flops have on their outputs the data received during receiving system clock cycles in which the toggle flip-flop toggled. If the toggle flip-flop did not toggle during a particular receiving system clock cycle, no data valid signal is produced because this data is either redundant or uncertain due to insufficient guaranteed setup time.

Application Number:
Publication Date:
November 29, 1995
Filing Date:
June 22, 1990
Export Citation:
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International Classes:
H04L7/00; H04L7/02; (IPC1-7): H04L7/00
Attorney, Agent or Firm:
Toshiaki Morisaki