Title:
【発明の名称】半導体記憶装置およびその製造方法
Document Type and Number:
Japanese Patent JPH0831569
Kind Code:
B2
Abstract:
A semiconductor region of a first conductivity type is formed in a column configuration on a semiconductor substrate, and acts as a source region (or a drain region) and a storage node electrode. A second semiconductor region of the first conductivity type is formed with a capacitor insulation film disposed between it and the side wall of the first semiconductor region and acts as a cell plate electrode. A third semiconductor region of a second conductivity type which is formed in an annular configuration is formed on the upper portion of the first semiconductor region and acts as a channel region. A first conductive layer is formed with a gate insulation film disposed between the first conductive layer and each of the inner and outer side walls of the third semiconductor region and acts as a transfer gate electrode. A fourth semiconductor region of the first conductivity type is formed in an area near the end portion of the opening of the third semiconductor region which is formed in the annular configuration and acts as a drain region (or a source region). A second conductive layer is formed in contact with the fourth semiconductor region and acts as a bit line.
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Inventors:
YOSHIDA TOORU
Application Number:
JP1123290A
Publication Date:
March 27, 1996
Filing Date:
January 20, 1990
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L27/10; H01L21/8242; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242
Domestic Patent References:
| JP6366963A | ||||
| JP1125858A |
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)