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Document Type and Number:
Japanese Patent JPS5753888
Kind Code:
A dynamic read amplifier for MOS memories comprises a flip-flop which includes two first switching transistors whose low end can be applied to ground by way of a cut-through transistor in response to a first clock pulse and whose outputs are connected to data lines via cut-off transistors which are controlled by a second clock pulse, whereby the data lines can be charged to the supply voltage by way of a pair of charging transistors in response to a third clock pulse. Given such dynamic read amplifiers for semiconductor memories, the regeneration of a logic "1" level, for example, is possible after an evaluation operation without additional leakage power. Therefore, two additional switching transistors and two further charging transistors are provided, as well as two additional data lines, so that only the respective data line with the logic "1" signal is connected to the supply voltage. By so doing, even given dynamic read amplifiers, the read logic "1" signal can again be completely regenerated and, at the same time, the switching time for the data is reduced.

Application Number:
Publication Date:
March 31, 1982
Filing Date:
July 28, 1981
Export Citation:
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International Classes:
G11C11/419; G11C11/409; G11C11/4091; (IPC1-7): G11C7/06; G11C11/34
Domestic Patent References: