Title:
DIGITAL DATA PROCESSOR WITH FAULT TOLERANT BUS PROTOCOL
Document Type and Number:
Japanese Patent JPS58137056
Kind Code:
A
Abstract:
A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit (12) and a memory unit (16) and one or more peripheral control units (20, 24), on a bus structure (30) common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner (14, 18, 22, 26). Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.
Inventors:
GAADONAA SHII HENDORII
KURUTO EFU BEITEI
RONARUDO II DEINESON
DANIERU EMU FUOOKOFU
ROBAATO RIIDO
JIYOZEFU II SAMUSON
KENESU TEII URUFU
KURUTO EFU BEITEI
RONARUDO II DEINESON
DANIERU EMU FUOOKOFU
ROBAATO RIIDO
JIYOZEFU II SAMUSON
KENESU TEII URUFU
Application Number:
JP16995982A
Publication Date:
August 15, 1983
Filing Date:
September 30, 1982
Export Citation:
Assignee:
STRATUS COMPUTER INC
International Classes:
G06F1/04; G06F3/00; G06F11/00; G06F11/14; G06F11/16; G06F11/18; G06F11/20; G06F11/22; G06F13/00; (IPC1-7): G06F3/00; G06F11/20
Domestic Patent References:
| JPS5280753A | 1977-07-06 | |||
| JPS559226A | 1980-01-23 | |||
| JPS5533213A | 1980-03-08 | |||
| JPS5386537A | 1978-07-31 | |||
| JPS5186335A | 1976-07-28 |
Attorney, Agent or Firm:
Motohiro Kurauchi