Title:
３Ｄ電子モジュールの小型化チップオンチップ相互接続の方法
Document Type and Number:
Japanese Patent JP6873147
Kind Code:
B2
Abstract:
The invention relates to a 3D electronic module including, in a direction referred to as the vertical direction, a stack (4) of electronic dice (16), each die including at least one chip (1) provided with interconnect pads (10), this stack being attached to an interconnect circuit (2) for the module provided with connection bumps, the pads (10) of each chip being connected by electrical bonding wires (15) to vertical buses (41) that are themselves electrically linked to the interconnect circuit (2) for the module, a bonding wire and the vertical bus to which it is linked forming an electrical conductor between a pad of a chip and the interconnect circuit, characterized in that each electrical bonding wire (15) is linked to its vertical bus (41) by forming, in a vertical plane, an oblique angle (α2) and in that the length of the bonding wire between a pad of a chip of one die and the corresponding vertical bus is different than the length of the bonding wire between one and the same pad of a chip of another die and the corresponding vertical bus, and this is obtained by wiring the bonding wire in a non-rectilinear manner to compensate for the difference in vertical length of the vertical bus from one die to the other, such that the electrical conductor between the pad of a chip of one die and the interconnect circuit, and the electrical conductor between said same pad of a chip of the other die and the interconnect circuit, are the same length.
Inventors:
Bar, Christian
Application Number:
JP2018543640A
Publication Date:
May 19, 2021
Filing Date:
February 14, 2017
Export Citation:
Assignee:
Threed Plus
International Classes:
H01L25/065; H01L21/60; H01L25/07; H01L25/18
Domestic Patent References:
| JP2011029581A | ||||
| JP2008109005A | ||||
| JP9232503A | ||||
| JP5283608A |
Foreign References:
| US20150001739 | ||||
| US20060000876 |
Attorney, Agent or Firm:
Kawaguchi International Patent Office