Title:
576KHZ CLOCK GENERATION CIRCUIT
Document Type and Number:
Japanese Patent JPH0653952
Kind Code:
A
Abstract:
PURPOSE: To provide a small-sized 576kHz clock generation circuit with high reliability by constituting the clock generation circuit with a digital circuit relating to a circuit for generating 576kHz clocks by frequency-dividing the clocks of a frequency 19.44MHz.
CONSTITUTION: This circuit is provided with a frequency divider circuit 10 for 33-frequency dividing and 34-frequency dividing the clocks of the frequency 19.44MHz and a control circuit 20 for synchronizing with 8kHz frame pulses and controlling the frequency dividing operation of the frequency divider circuit 10. Then, the 576kHz clocks synchronized with the 8kHz frame pulses are generated.
Inventors:
SEKIYAMA SHIGEO
Application Number:
JP20581592A
Publication Date:
February 25, 1994
Filing Date:
August 03, 1992
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H04L7/08; (IPC1-7): H04L7/08
Attorney, Agent or Firm:
Teiichi
Next Patent: FRAME SYNCHRONISM PROTECTIVE CIRCUIT