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Title:
ADDRESS DESIGNATION DEVICE FOR MEMORY
Document Type and Number:
Japanese Patent JPS5810252
Kind Code:
A
Abstract:

PURPOSE: To simplify a processing program and to decrease the memory capacity, by introducing an absolute address from the 2nd absolute address, based on the information discriminating the 1st absolute address and a terminal device fixedly set.

CONSTITUTION: A storage area (page) for the data processing by a terminal device of an RAM 30 is designated for the address with, e.g., 8-digit figure and address designation is made with the combination of the absolute address consisting of a figure of upper-order 2-digit and a relative address consisting of a figure of lower-order 2-digit. An interruption request signal terminal of an interruption code converting circuit 14 is connected to an interruption request signal input terminal of a CPU 11. The interruption code conversion circuit 14 provides an interruption request signal INT to the CPU 11 when the interruption request is given from transmission control circuits 151W15N to give a code discriminating a terminal device based on the interruption request from any terminal device to a page code conversion circuit 20.


Inventors:
SAITOU SATORU
Application Number:
JP10850181A
Publication Date:
January 20, 1983
Filing Date:
July 11, 1981
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G06F9/355; G06F12/00; G06F12/02; G06F12/06; G06F13/24; (IPC1-7): G06F9/36; G06F9/46; G06F13/00; G11C8/00
Attorney, Agent or Firm:
Kuro Fukami