Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ALL-OPTICAL MEMORY LATCH
Document Type and Number:
Japanese Patent JP2009104212
Kind Code:
A
Abstract:

To provide an all-optical memory latch.

An all-optical memory latch includes: a first logic gate configured to receive a first input signal, a third input signal and continuous wave (CW) light, wherein the first logic gate includes: a first nonlinear element that performs logic operation relating to the binary logic levels of the first and third input signals and generates a first output signal; and a second nonlinear element that has an optical resonator comprising a material having a refractive index depending on the intensity tuned to the resonant frequency so as to perform logic operation relating to the binary logic levels of the first output signal and the CW light through nonlinear discrimination of their combined intensity. The second nonlinear element includes: a first logic gate resuming an enhanced binary logic level of the first output signal by using the CW light; and a second logic gate receiving a second input signal, a fourth input signal and CW light to output a second output signal. The first output signal is guided as the fourth input signal to the second logic gate; while the second output signal is guided as the third input signal to the first logic gate.


Inventors:
COVEY JOHN LUTHER
Application Number:
JP2009000035701
Publication Date:
May 14, 2009
Filing Date:
February 18, 2009
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
COVEYTECH LLC
International Classes:
G02F3/00; G02B1/02; G02B6/12; G02F1/365
Domestic Patent References:
JPH032845A1991-01-09
JPS62269125A1987-11-21
JPH095812A1997-01-10
Attorney, Agent or Firm:
青木 篤
鶴田 準一
水谷 好男
宮本 哲夫
森 啓