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Patent Searching and Data


Title:
AMPLIFICATION CIRCUIT
Document Type and Number:
Japanese Patent JPH03256295
Kind Code:
A
Abstract:

PURPOSE: To speed up the operation of an amplification circuit by activating and deactivating a current miller type sense amplifier when an input clock signal is enable and disable respectively.

CONSTITUTION: In a usual operation state, a clock signal, the inverse of CLK is 'L' level, and the current miller type sense amplifier 101 is activated. At that time, a transistor (TR) M13 for pull-down is kept turned OFF, and a large amplitude level appears in the outputs 11, 12 of the amplifier 101 according to an input signal IN and the inverse of IN. Then, one of the TRs Q11, M11 of a buffer part is turned ON, and the other one is turned OFF, and the level of 'H' or 'L' appears in an output terminal. Here, the signal, the inverse of CLK is controlled, and the amplifier 101 is deactivated, and its output is pulled down to earth potential. Thus, even if a logic circuit is not added, the operation of the amplification circuit can be speeded up while realizing an output try statizing function.


Inventors:
KOBAYASHI YASUO
Application Number:
JP5543190A
Publication Date:
November 14, 1991
Filing Date:
March 06, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
G11C11/419; G11C11/409; H03K5/02; H03K19/0175; H03K19/08; (IPC1-7): G11C11/419; H03K5/02; H03K19/0175; H03K19/08