Title:
アナログデジタル変換器
Document Type and Number:
Japanese Patent JP4652214
Kind Code:
B2
Abstract:
Included are a first unit including a DAC which generates a comparison signal serving as an object of comparison with the first analog signal, taking in and retaining the first analog signal, a second unit including a DAC which generates a comparison signal serving as an object of comparison with the first analog signal, taking in and retaining the second analog signal, a first switch connecting the first unit to an output side of the second unit, a comparator comparing a differential value between the first analog signal and the second analog signal with a differential value between the comparison signal of the first DAC and an output signal of the second DAC, and an electric potential control circuit controlling fluctuations in electric potentials of the first analog terminal and the second analog terminal.
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Inventors:
Tachibana Dai
Kazuhiro Mitsuda
Tatsuo Kato
Kazuhiro Mitsuda
Tatsuo Kato
Application Number:
JP2005334563A
Publication Date:
March 16, 2011
Filing Date:
November 18, 2005
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
H03M1/38
Domestic Patent References:
| JP58170119A |
Other References:
Gilbert Promitzer,12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s,IEEE Journal of Solid-State Circuits,米国,2001年 7月,Volume36, Issue7 ,Pages1138-1143
Bienstman, L.A.; De Man, H.J.; ,An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling,IEEE Journal of Solid-State Circuits,米国,1980年12月,Vol.SC-15, No.6,Pages1051-1059
Bienstman, L.A.; De Man, H.J.; ,An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling,IEEE Journal of Solid-State Circuits,米国,1980年12月,Vol.SC-15, No.6,Pages1051-1059
Attorney, Agent or Firm:
Hidemi Matsukura
Akira Hirakawa
Daisuke Takada
Tsutomu Toyama
Akira Hirakawa
Daisuke Takada
Tsutomu Toyama